PCB Factory Impedance Control Guidelines

Impedance control purpose

To determine the requirements of impedance control, to standardize the impedance calculation method, to formulate the guidelines of impedance test COUPON design, and to ensure that the products can meet the needs of production and customer requirements.

Definition of impedance control

Definition of impedance

At a certain frequency, the electronic device transmission signal line, relative to a reference layer, its high-frequency signal or electromagnetic wave in the propagation process of resistance is called characteristic impedance, it is a vector sum of electrical impedance, inductive resistance, capacitive resistance .......

Classification of impedance

At present, our common impedance is divided into: single-ended (line) impedance, differential (dynamic) impedance, common

Impedance of these three cases

• Single-ended (line) impedance: English single ended impedance, refers to the impedance measured by a single signal line.
• Differential (dynamic) impedance: English differential impedance, refers to the differential drive in the two equal-width, equal-spaced transmission lines tested to the impedance.
• Coplanar impedance: English coplanar impedance, refers to the signal line in its surrounding GND / VCC (signal line to its two sides of GND / VCC The impedance tested when the transmission between the GND/VCC (equal distance between the signal line to its two sides GND/VCC).

Impedance control requirements are determined by the following conditions

When the signal is transmitted in the PCB conductor, if the length of the wire is close to 1/7 of the signal wavelength, then the wire becomes a signal

PCB production, according to customer requirements to decide whether to control the impedance

If the customer requires a line width to do impedance control, the production needs to control the impedance of the line width.

Three elements of impedance matching:

Output impedance (original active part), characteristic impedance (signal line), and input impedance (passive part)

(PCB board) impedance matching

When the signal is transmitted on the PCB, the characteristic impedance of the PCB board must match the electronic impedance of the head and tail components. Once the impedance value is out of tolerance, the transmitted signal energy will be reflected, scattered, attenuated or delayed, resulting in an incomplete signal and signal distortion. Impedance influencing factors:

Er: dielectric permittivity, inversely proportional to the impedance value , dielectric constant according to the newly provided "sheet dielectric constant table" calculation .

H1, H2, H3, etc.: line layer and grounding layer between the media thickness, and impedance value is proportional.

W1: impedance line line width; W2: impedance line width, and impedance is inversely proportional.

A: when the inner bottom copper for HOZ, W1 = W2 + 0.3mil; inner bottom copper for 1OZ, W1 = W2 + 0.5mil; when the inner bottom copper for 2OZ W1 = W2 + 1.2mil.

B: When the outer base copper is HOZ, W1=W2+0.8mil; when the outer base copper is 1OZ, W1=W2+1.2mil; when the outer base copper is 2OZ, W1=W2+1.6mil.

C: W1 is the original impedance line width. T: copper thickness, inversely proportional to the impedance value.

A: The inner layer is the substrate copper thickness, HOZ is calculated by 15μm; 1OZ is calculated by 30μm; 2OZ is calculated by 65μm.

B: The outer layer is copper foil thickness + copper plating thickness, depending on the hole copper specifications, when the bottom copper is HOZ, hole copper (average 20μm, minimum 18μm ), the table copper calculated by 45μm; hole copper (average 25μm, minimum 20μm), the table copper calculated by 50μm; hole copper single point minimum 25μm, the table copper calculated by 55μm.

C: When the bottom copper is 1OZ, hole copper (average 20μm, minimum 18μm), the table copper is calculated by 55μm; hole copper (average 25μm, minimum 20μm), the table copper is calculated by 60μm; hole copper single point minimum 25μm, the table copper is calculated by 65μm.

S: the spacing between adjacent lines and lines, proportional to the impedance value (differential impedance).

• C1: substrate solder resistance thickness, inversely proportional to the impedance value;
• C2: line surface solder resistance thickness, inversely proportional to the impedance value;
• C3: interline thickness, inversely proportional to the impedance value;
• CEr: solder resist dielectric constant, and the impedance value is inversely proportional to .

A: Printed once solder resist ink, C1 value of 30μm, C2 value of 12μm, C3 value of 30μm.

B: Printed twice solder resist ink, C1 value of 60μm, C2 value of 25μm, C3 value of 60μm.

C: CEr: calculated according to 3.4.

Scope of application:Differential impedance calculation before outer resistance welding

Parameter Description.

H1:Dielectric thickness between outer layer and VCC/GND

W2:Impedance line surface width

W1:Bottom width of impedance line

S1:Differential impedance line gap

Er1:dielectric layer dielectric constant

T1:Line copper thickness, including substrate copper thickness + plating copper thickness

Scope of application:Differential impedance calculation after outer resistance welding

Parameter Description.

H1:Thickness of dielectric between outer layer and VCC/GND

W2:Impedance line surface width

W1:Bottom width of impedance line

S1:Differential impedance line gap

Er1:dielectric layer dielectric constant

T1:Line copper thickness, including substrate copper thickness + plating copper thickness

CEr:Impedance dielectric constant

C1:Substrate resist thickness

C2:Line surface resist thickness

C3:Differential impedance interline resist thickness

Design of impedance test COUPON

COUPON add location

Impedance test COUPON is generally placed in the middle of the PNL, not allowed to be placed on the edge of the PNL board, except in special cases (such as 1PNL = 1PCS).

COUPON design considerations

To ensure the accuracy of impedance test data, COUPON design must completely simulate the form of the line inside the board, if the impedance line around the board is protected by copper, the COUPON should be designed to replace the protection line; if the board resistance line is "snake" alignment, the COUPON also needs to be designed as a "snake" alignment. If the resistance line in the board is "snake" alignment, then the COUPON should also be designed as "snake" alignment.

Impedance test COUPON design specifications

Single-ended (line) impedance:

Test COUPON main parameters:

• A: test hole diameter ∮ 1.20MM (2X/COUPON), this is the size of the tester probe
• B: test positioning hole: unified by ∮2.0MM production (3X/COUPON), gong board positioning with; C: two test hole spacing of 3.58MM

Differential (dynamic) impedance

Test COUPON main parameters: A: test hole diameter ∮ 1.20MM (4X/COUPON), two of them for the signal hole, the other two for the grounding hole, are the size of the tester probe; B: test positioning hole: unified according to the production of ∮ 2.0MM (3X/COUPON), gong board positioning with; C: two signal hole spacing: 5.08MM, two grounding hole spacing for: 10.16MM.

Design COUPON notes

• The distance between the protection line and the impedance line needs to be greater than the width of the impedance line .
• Impedance line length is generally designed in the range of 6-12INCH.
• The nearest GND or POWER layer of the adjacent signal layer is the ground reference layer for impedance measurement.
• The protection line of the signal line added between the two GND and POWER should not obscure the signal line of any layer between GND and POWER layers.
• The two signal holes lead to the differential impedance line, and the two ground holes must be grounded at the same time in the reference layer.
• In order to ensure the uniformity of copper plating, it is necessary to add a power grabbing PAD or copper skin in the outer empty board position.

Differential coplanar impedance

Test COUPON main parameters: the same differential impedance

Differential coplanar impedance type:

• Reference layer and impedance line in the same level, that is, the impedance line is surrounded by the surrounding GND / VCC, the surrounding GND / VCC is the reference level. POLAR software calculation mode, see 4.5.3.8; 4.5.3.9; 4.5.3.12.
• The reference layer is the GND/VCC on the same level and the GND/VCC layer adjacent to the signal layer. (The impedance line is surrounded by the surrounding GND/VCC, and the surrounding GND/VCC is the reference layer).